The present invention pertains to frequency dividers and methods therefor and in particular to synchronous carry frequency dividers using a series of counters and methods therefor.
Phase-locked loop and frequency synthesis applications often require the use of frequency dividers having a high frequency capability. Digital frequency dividers are commonly implemented by a programmable counter having a gating structure which provides an output pulse after a programmed number of input pulses have been received. This output pulse is used both to provide an indication that the desired count has been reached and to enable reloading of the counter.
Digital frequency dividers often use a pulsed input signal to clock a counter the terminal count of which provides an output signal at a frequency equal to an integral submultiple, hereinafter referred to as the divide modulus, of the frequency of the pulsed input signal. Especially where the divide modulus is very large, it is impractical to implement a frequency divider using a single, commercially available counter.
One approach used in existing counters for providing a larger divide modulus involves linking several counters in series, carry output to carry input. When linked in this way the carry input line overrides the clock in order to allow several devices to be cascaded into a fully synchronous multi-stage counter. However, in this approach the carry signal associated with the last count must ripple through all of the counters from that containing the least significant bit to the counter containing the most significant bit within one clock period to provide the desired terminal count and to preset the counters for the next counting cycle. The propagation delay associated with the ripple carry technique severely restricts the maximum operating frequency of counters having a large divide modulus.
One approach to overcoming the delays associated with the ripple carry technique involves the use of an external decoding network. In this approach, a gate is used with each counter to decode the terminal count condition one clock pulse before the zero state of the counter so that the clock pulse necessary for presetting is included in the programmed input number. Thus, in order to detect the terminal count the decode network approach requires a reasonably complex terminal count decode network. In addition to externally decoding the preset condition, a pulse "gobbling" technique may be used wherein the terminal count is detected two clock pulses before the zero state of the counter but wherein an external flip-flop in series with the decoding gate holds a pulse until one clock pulse before the zero state of the counter. In this way an even shorter preset delay time is achieved because the decoded delay and the set up time for presetting the counter do not have to occur within one clock period but rather occur within separate clock periods. Nevertheless, for large modulus dividers a reasonably complex terminal count decode network is required which increases the cost and complexity of the divider. Furthermore, the external decoding approach introduces a delay of its own which may need to be compensated for by pulse gobbling or some other technique in order to achieve high frequency counters.
It is therefore desirable to provide a frequency divider which does not require the cost and complexity of external decoding and yet which does not possess the delay of ripple carry dividers.